/* This interrupt is generated when HSE clock fails */ if (RCC_GetITStatus(RCC_IT_CSS) != RESET) { /* At this stage: HSE, PLL are disabled (but no change on PLL config) and HSI is selected as system clock source */
/* Clear Clock Security System interrupt pending bit */ RCC_ClearITPendingBit(RCC_IT_CSS);
/* Once HSE clock recover, the HSERDY interrupt is generated and in the RCC ISR routine the system clock will be reconfigured to its previous state (before HSE clock failure) */ }
以下是英文原文供对照 Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex™-M3 NMI (Non-Maskable Interrupt) exception vector.
Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt register (RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.
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STM32 发表于 2007-12-26 22:46 
